Apparatus and method for electrolytically depositing copper on a semiconductor workpiece

ABSTRACT

A process for applying a metallization interconnect structure to a semiconductor workpiece having a barrier layer deposited on a surface thereof is set forth. The process includes the forming of an ultra-thin metal seed layer on the barrier layer. The ultra-thin seed layer having a thickness of less than or equal to about 500 Angstroms. The ultra-thin seed layer is then enhanced by depositing additional metal thereon to provide an enhanced seed layer. The enhanced seed layer has a thickness at all points on sidewalls of substantially all recessed features distributed within the workpiece that is equal to or greater than about 10% of the nominal seed layer thickness over an exteriorly disposed surface of the workpiece.

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] Not Applicable

STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT NotApplicable BACKGROUND OF THE INVENTION

[0002] An integrated circuit is an interconnected ensemble of devicesformed within a semiconductor material and within a dielectric materialthat overlies a surface of the semiconductor. Devices which may beformed within the semiconductor include MOS transistors, bipolartransistors, diodes and diffused resistors Devices which may be formedwithin the dielectric include thin-film resistors and capacitorsTypically, more than 100 integrated circuit die (IC chips) areconstructed on a single 8 inch diameter silicon wafer. The devicesutilized in each dice are interconnected by conductor paths formedwithin the dielectric. Typically, two or more levels of conductor paths,with successive levels separated by a dielectric layer, arc employed asinterconnections. In current practice, an aluminum alloy and siliconoxide are typically used for, respectively, the conductor anddielectric.

[0003] Delays in propagation of electrical signals between devices on asingle die limit the performance of integrated circuits. Moreparticularly, these delays limit the speed at which an integratedcircuit may process these electrical signals. Larger propagation delaysreduce the speed at which the integrated circuit may process theelectrical signals, while smaller propagation delays increase thisspeed. Accordingly, integrated circuit manufacturers seek ways in whichto reduce the propagation delays.

[0004] For each interconnect path, signal propagation delay may becharacterized by a time delay τ. See E. H. Stevens, InterconnectTechnology, QMC, Inc., July 1993. An approximate expression for the timedelay, τ, as it relates to the transmission of a signal betweentransistors on an integrated circuit is given below.τ = RC[1 + (V_(SAT) + RI_(SAT))]

[0005] In this equation, R and C are, respectively, an equivalentresistance and capacitance for the interconnect path and I_(SAT) andV_(SAT) are, respectively, the saturation (maximum) current and thedrain-to-source potential at the onset of current saturation for thetransistor that applies a signal to the interconnect path The pathresistance is proportional to the resistivity, ρ, of the conductormaterial. The path capacitance is proportional to the relativedielectric permittivity, K₄, of the dielectric material. A small valueof τ requires that the interconnect line carry a current densitysufficiently large to make the ratio V_(SAT) small. It followstherefore, that a low-ρ conductor which can carry a high current densityand a low-K_(c) dielectric must be utilized in the manufacture ofhigh-performance integrated circuits.

[0006] To meet the foregoing criterion copper interconnect lines withina low-K₉₆ dielectric will likely replace aluminum-alloy lines within asilicon oxide dielectric as the most preferred interconnect structure.See “Copper Goes Mainstream. Low-k to Follow”, SemiconductorInternational, November 1997, pp. 67-70. Resistivities of copper filmsare in the range of 1.7 to 2.0 μΩcm; resistivities of aluminum-alloyfilms are in the range of 3.0 to 3.5 μΩcm.

[0007] Despite the advantageous properties of copper, it has not been aswidely used as an interconnect material as one would expect. This isdue, at least in part to the difficulty of depositing coppermetallization and, further, due to the need for the presence of barrierlayer materials. The need for a barrier layer arises from the tendencyof copper to diffuse into silicon junctions and alter the electricalcharacteristics of the semiconductor devices formed in the substrate.Barrier layers made of, for example, titanium nitride, tantalum nitride,etc., must be laid over the silicon junctions and any intervening layersprior to depositing a layer of copper to prevent such diffusion.

[0008] A number of processes for applying copper metallization tosemiconductor workpieces have been developed in recent years. One suchprocess is chemical vapor deposition (CVD), in which a thin copper filmis formed on the surface of the barrier layer by thermal decompositionand/or reaction of gas phase copper compositions. A CVD process canresult in conformal copper coverage over a variety of topologicalprofiles, but such processes are expensive when used to implement anentire metallization layer.

[0009] Another known technique, physical vapor deposition (PVD), canreadily deposit copper on the barrier layer with relatively goodadhesion when compared to CVD processes. One disadvantage of PVDprocesses, however, is that they result in poor (non-conformal) stepcoverage when used to fill microstructures, such as vias and trenches,disposed in the surface of the semiconductor workpiece For example, suchnon-conformal coverage results in less copper deposition at the bottomand especially on the sidewalls of trenches in the semiconductordevices.

[0010] Inadequate deposition of a PVD copper layer into a trench to forman interconnect line in the plane of a metallization layer isillustrated in FIG. 1. As illustrated, the upper portion of the trenchis effectively “pinched off” before an adequate amount of copper hasbeen deposited within the lower portions of the trench. This result inan open void region that seriously impacts the ability of themetallization line to carry the electrical signals for which it wasdesigned.

[0011] Electrochemical deposition of copper has been found to providethe most cost-effective manner in which to deposit a coppermetallization layer. In addition to being economically viable, suchdeposition techniques provide substantially conformal copper films thatare mechanically and electrically suitable for interconnect structures.These techniques, however, are generally only suitable for applyingcopper to an electrically conductive layer. As such, an underlyingconductive seed layer is generally applied to the workpiece before it issubject to an electrochemical deposition process. Techniques forelectrodeposition of copper on a barrier layer material have notheretofore been commercially viable.

[0012] The present inventors have recognized that there exists a need toprovide copper metallization processing techniques that 1) provideconformal copper coverage with adequate adhesion to the barrier layer,2) provide adequate deposition speeds, and 3) arc commercially viable.These needs are met by the apparatus and processes of the presentinvention as described below.

BRIEF SUMMARY OF THE INVENTION

[0013] A process for applying a metallization interconnect structure toa semiconductor workpiece having a barrier layer deposited on a surfacethereof is set forth. The process includes the forming of an ultra-thinmetal seed layer on the barrier layer The ultra-thin seed layer having athickness of less than or equal to about 500 Angstroms The ultra-thinseed layer is then enhanced by depositing additional metal thereon toprovide an enhanced seed layer. The enhanced seed layer has a thicknessat all points on sidewalls of substantially all recessed featuresdistributed within the workpiece that is equal to or greater than about10% of the nominal seed layer thickness over an exteriorly disposedsurface of the workpiece.

[0014] In accordance with a specific embodiment of the process, a coppermetallization interconnects structure is formed. To this end, theultra-thin seed layer is enhanced by subjecting the semiconductorworkpiece to an electrochemical copper deposition process in which analkaline bath having a complexing agent is employed. The coppercomplexing agent may be at least one complexing agent selected from agroup consisting of EDTA, ED, and a polycarboxylic acid such as citricacid or salts thereof.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

[0015]FIG. 1 is a cross-sectional view illustrating an interconnect lineformed completely by PVD copper.

[0016] FIGS. 2A-2F are cross-sectional views through a semiconductorworkpiece illustrating the various layers of material as they areapplied in accordance with one embodiment of the present invention.

[0017]FIG. 3 is a schematic representation of an apparatus suitable forenhancing an ultra-thin seed layer.

[0018]FIG. 4A is a graph illustrating the current-potential curves of aplating solution using a polycarboxylic acid, such as citric acid, as acompleting agent.

[0019]FIG. 4B a graph illustrating the current-potential curves of aplating solution using EDTA, an amine-containing plating solution, asthe complexing agent.

[0020]FIG. 5 is a scanning eletromicrograph photograph illustrating anultra-thin seed layer.

[0021]FIG. 6A is a scanning eletromicrograph photograph illustrating anultra-thin seed layer that has been enhanced in a citric acid bath.

[0022]FIG. 6B is a scanning eletromicrograph photograph illustrating anultra-thin seed layer that has been enhanced in an EDTA bath.

[0023]FIG. 7 is a schematic representation of a section of asemiconductor manufacturing line suitable for implementing the disclosedseed layer enhancement steps.

DETAILED DESCRIPTION OF THE INVENTION

[0024] This invention employs a novel approach to the coppermetallization of a semiconductor article resulting in a copper layerthat is uniformly deposited in a conformal coating on the barrier layerwith good adhesion to the barrier layer. In accordance with theinvention, an alkaline electrolytic copper bath is used to enhance anultra-thin copper seed layer which has been deposited on the barrierlayer using a deposition process such as PVD. The enhanced copper seedlayer provides an excellent conformal copper coating that allowstrenches and vias to be subsequently filled with a copper layer havinggood uniformity using electrochemical deposition techniques.

[0025] A cross-sectional view of a micro-structure, such as trench 5,that is to be filled with copper metallization is illustrated in FIG.2A. As shown, a thin barrier layer 10 of, for example, titanium nitrideor tantalum nitride is deposited over the surface of a semiconductordevice or, as illustrated in FIG. 2A. over a layer of a dielectric 8,such as silicon dioxide. The barrier layer 10 acts to prevent themigration of copper to any semiconductor device formed in the substrate.Any of the various known techniques, such as CVD or PVD, can be used todeposit the barrier layer depending on the particular barrier materialbeing used. Preferably, the thickness for the barrier layer isapproximately 100 to 300 Angstroms.

[0026] After the deposition of the barrier layer, an ultra-thin copperseed layer 15 is deposited on the barrier layer 10. The resultingstructure is illustrated in FIG. 2B. Preferably, the copper seed layer15 is formed using a vapor deposition technique, such as CVD or PVD. Inorder to have adequate adhesion and copper coverage, a relatively thick(1000 Angstroms) copper seed layer is usually required. Such a thickseed layer leads to problems with close-off of small geometry trenches,however, when a PVD deposition process is employed for applying the seedlayer.

[0027] Contrary to traditional thoughts regarding seed layerapplication, the copper seed layer 15 of the illustrated embodiment isultra-thin, having a thickness of about 50 to about 500 Angstroms,preferably about 100 to about 250 Angstroms, and most preferably about200 Angstroms. The ultra-thin copper seed layer can be deposited using aCVD or a PVD process, or a combination of both. PVD is the preferredapplication process, however, because it can readily deposit copper onthe barrier layer 10 with relatively good adhesion. By depositing anultra-thin seed layer of copper, rather than the relatively thick seedlayer used in the prior art, pinching off of the trenches can beavoided.

[0028] The use of an ultra-thin seed layer 15 generally introduces itsown set of problems. One of the most significant of these problems isthe fact that such ultra-thin layers do not generally coat the barrierlayer 10 in a uniform manner. Rather, voids or non-continuous seed layerregions on the sidewalls, such as at 20, are often present in anultra-thin seed layer 15 thereby resulting in the inability to properlyapply a subsequent electrochemically deposited copper layer in theregions 20. Further, ultra-thin seed layers tend to include spikes, suchas at 21, that impact the uniformity of the subsequent electrolyticallydeposited metal layer. Such spikes 21 result in high potential regionsat which the copper deposits at a higher rate than at other, more levelregions. As such, the seed layer 15 is not fully suitable for thetraditional electroplating techniques typically used after applicationof a seed layer.

[0029] The present inventors have found that an ultra-thin seed layercan be employed if it is combined with a subsequent electrochemical seedlayer enhancement technique. To this end, the semiconductor workpiece issubject to a subsequent process step in which a further amount of copper18 is applied to the ultra-thin seed layer to thereby enhance the seedlayer. A seed layer enhanced by the additional deposition of copper isillustrated in FIG. 2C. As shown in FIG. 2C, the void or non-continuousregions 20 of FIG. 2B have been filled thereby leaving substantially allof the barrier layer 10 covered with copper.

[0030] Preferably, the seed layer enhancement process continues until asidewall step coverage, i.e., the ratio of the seed layer thickness atthe bottom sidewall regions 22 to the nominal thickness of the seedlayer at the exteriorly disposed side 23 of the workpiece, achieves avalue of at least 10%. More preferably, the sidewall step coverage is atleast about 20%. Such sidewall step coverage values are present insubstantially all of the recessed structures of the semiconductorworkpiece. It will be recognized, however, that certain recessedstructures distributed within the semiconductor workpiece may not reachthese sidewall step coverage values. For example, such structuresdisposed at the peripheral edges of a semiconductor wafer may not reachthese step coverage values. Similarly, defects or contaminants at thesitus of certain recessed structures may prevent them from reaching thedesired coverage values. The nominal thickness of the enhanced seedlayer at the exteriorly disposed side of the workpiece is preferably inthe range of 500 angstroms 1600 angstroms.

[0031] Although the embodiment of the process disclosed herein isdescribed in connection with copper metallization, it is understood thatthe basic principle of the enhancement of an ultra-thin seed layer priorto the bulk deposition thereof can be applied to other metals or alloysthat are capable of being electroplated. Such metals include iron,nickel, cobalt, zinc, copper-zinc, nickel-iron, cobalt-iron, etc.

[0032] A schematic representation of an apparatus 25 suitable forenhancing the ultra-thin copper seed layer is illustrated in FIG. 3. Asshown, a semiconductor workpiece, such as a semiconductor wafer 30, ispositioned face down in a bath 35 of electroplating solution. One ormore contacts 40 are provided to connect the wafer 30 to a plating powersupply 45 as a cathode of an electroplating cell. An anode 50 isdisposed in the bath 35 and is connected to the plating power supply 45.Preferably, a diffuser 55 is disposed between the anode 50 and thewafer/cathode 30. The wafer 30 may be rotated about axis 60 during theenhancement process. Anode 50 may be provided with a dielectric shield65 at a backside thereof which faces an incoming stream of plating bathfluid.

[0033] The electrolytic bath solution for enhancing the seed layer is analkaline copper bath in which copper ions are complexed with acomplexing agent. A preferred source of copper ions is copper sulfate(CuSO₄). The concentration of copper sulfate in the bath is preferablywithin the range of 0.03 to 0.25 M, and is more preferably about 0.1 M.

[0034] Complexing agents that are suitable for use in the presentinvention form a stable complex with copper ions and prevent theprecipitation of copper hydroxide. Ethylene diamine tetracetic acid(EDTA), ethylene diamine (ED), citric acid, and their salts have beenfound to be particularly suitable copper complexing agents The molarratio of complexing agent to copper sulfate in the bath is preferablywithin the range of 1 to 4. and is preferably about 2. Such complexingagents can be used alone, in combination with one another, or incombination with one or more further complexing agents.

[0035] The electrolytic bath is preferably maintained at a pH of atleast 9.0. Potassium hydroxide, ammonium hydroxide, or sodium hydroxideis utilized to adjust and maintain the pH at the desired level of 9.0 orabove. A preferred pH for a citric acid or ED bath is about 9.5, while apreferred pH for an EDTA bath is about 12.5

[0036] Additional components can be added to the alkaline copper bathFor example, boric acid (H₃BO₃) aids in maintaining the pH at 9.5 whencitric acid or ED is used as the complexing agent, and provides brightercopper deposits when added to an electrolytic bath containing EDTA asthe complexing agent. If boric acid is added, its concentration in thebath is preferably within the range of 0.01 to 0.5 M.

[0037] In general, the temperature of the bath can be within the rangeof 20 to 35° C., with 25° C. being a preferred temperature. The currentdensity for electrolytically depositing copper to enhance the copperseed layer can be 1 to 5 miliamps/cm², while a plating time of about 1to about 5 minutes is sufficient to enhance the copper seed layer. Theplating waveform may be, for example, a forward periodic pulse having aperiod of 2 msec at a 50% duty cycle.

[0038] An amine free acid complexing agent, for example, apolycarboxylic acid, such as citric acid, and salts thereof, ispreferable to the use of EDTA or ED. EDTA and ED include amine groups.These amine groups often remain on the surface of the semiconductorworkpiece after rinsing and drying of the wafer. Subsequent processes,particularly such processes as photolithographic processes, may becorrupted by the reactions resulting from the presence of these aminegroups. The amine groups may, for example, interfere with the chemicalreactions associated with th e exposing and/or curing of photoresistmaterials. As such, amine free complexing agents are particularlysuitable in processes in which a photolithographic process follows anelectrodeposition process.

[0039] A further advantage of using a polycarboxylic acid, such ascitric acid, stems from the fact that the magnitude of the voltagepotential at which the copper is plated is greater than the magnitude ofthe voltage potential at which the copper is plated in a bath containingEDTA. This is illustrated in FIGS. 4A and 4B where FIG. 4A is acurrent-potential graph for a citric acid bath, and FIG. 4B is acurrent-potential graph for an EDTA bath. Electroplating takes place atthe voltage where the corresponding current increases abruptly. Thisplating voltage is referred to as the deposition potential, which isapproximately −1.25 volts as shown in FIG. 4A for a bath employingcitric acid as the complexing agent, and is approximately −1.0 volts asshown in FIG. 4B for a bath employing EDTA as the complexing agent. Thecurrent peaks (70 70′ for the a bath containing a citric acid, and 72,72′ for the bath containing the EDTA) are the limiting currents whichare mainly determined by mass transfer and the concentration of copperions in the plating solutions. As illustrated, the magnitude of thecurrent and the particular plating potential is slightly dependent onthe substrate material. The different substrate results are illustratedin FIGS. 4A and 4B, where 70 and 72 are the curves for a coppersubstrate material, and 70′ and 72′ are curves for a copper substratematerial comprised of copper with a copper oxide coating. It is notedthat additional peaks occur on oxidized copper in the same electrolytes.These peaks are related to the electrochemical reduction of copper oxideto metallic copper before the alkaline electrochemical copperdeposition.

[0040] It is believed that a copper layer plated at a higher platingpotential in an alkaline bath provides greater adhesion to theunderlying barrier layer than a copper layer plated at a lower platingpotential in an acid bath. For copper to adhere to the barrier material,it is thought that copper ions must impinge on the barrier surface withsufficient energy to penetrate a thin oxidized or contaminated layer atthe barrier surface. It is therefore believed that a copper layerdeposited at a higher magnitude plating potential adhere is better tothe exposed barrier layer during the plating process when compared to alayer plated using a smaller magnitude plating potential. This factor,combined with the inter-copper chemical between the PVD copper and theelectrochemically deposited copper provides for an enhanced seed layerhaving excellent electrical as well as barrier adhesion properties.

[0041] With the seed layer enhanced in the foregoing manner, it issuitable for subsequent electrochemical copper deposition. Thissubsequent copper deposition may take place in an alkaline bath withinthe apparatus employed to enhance the seed layer. Preferably, however,subsequent copper deposition takes place in an acid environment whereplating rates are substantially higher than corresponding ratesassociated with alkaline plating baths. To this end, the semiconductorworkpiece is preferably transferred to an apparatus wherein theworkpiece is thoroughly rinsed with deionized water and then transferredto an apparatus similar to that of FIG. 3 wherein the plating bath isacidic. For example, one suitable copper bath comprises 170 g/l H₂SO₄,17 g/l copper and 70 ppm Chloride ions with organic additives. Theorganic additives are not absolutely necessary to the plating reaction.Rather, the organic additives may be used to produce desired filmcharacteristics and provide better filling of the recessed structures onthe wafer surface. The organic additives may include levelers,brighteners, wetting agents and ductility enhancers. It is during thisdeposition process that the trench 5 is substantially filled with afurther layer of electrochemically deposited copper 22. The resultingfilled cross-section is illustrated in FIG. 2D. After being filled inthis manner, the barrier layer and the copper layers disposed above thetrench are removed using any suitable process thereby leaving only thetrench 5 with the copper metallization and associated barrier materialas shown in FIG. 2E.

[0042] Use of an alkaline electrolytic bath to enhance the copper seedlayer has particular advantages over utilizing acid copper baths withoutseed layer enhancement- After deposition of the PVD copper seed layer,the copper seed layer is typically exposed to an oxygen-containingenvironment. Oxygen readily converts metallic copper to copper oxide. Ifan acid copper bath is used to plate copper onto the seed layer afterexposure of the seed layer to an oxygen containing environment, the acidcopper bath would dissolve copper oxide that had formed, resulting invoids in the seed layer and poor uniformity of the copper layerdeposited on the seed layer. Use of an alkaline copper bath inaccordance with the disclosed embodiment avoids the problem byadvantageously reducing any copper oxide at the surface of the seedlayer to metallic copper. Another advantage of the alkaline copper bathis that the plated copper has much better adhesion to the barrier layerthan that plated from an acid copper bath. Additional advantages of thepresent invention can be seen from the following Example.

EXAMPLE 1

[0043] Comparison of Acid Copper Plating With and Without Seed LayerEnhancement

[0044] Semiconductor wafers 1, 2 and 3 were each coated with a 200Angstrom PVD copper seed layer. In accordance with the presentinvention, wafers 1 and 2 had seed layer enhancement from citric acidand EDTA baths, respectively, the compositions of which are set forthbelow:

[0045] Bath for Wafer 1: 0.1 M Cu SO₄+0.2 M Citric acid+0.05 M H BO inD.I. water at pH 9.5, temperature 25° C.

[0046] Bath for Wafer 2: 0.1 M Cu SO₄+0.2 M EDTA acid+0.05 H BO in D.I.water at pH 12.5, temperature 25° C.

[0047] Wafer 3 did not have any seed layer enhancement.

[0048] The three wafers were then plated with a 1.5 micron copper layerfrom an acid copper bath under identical conditions. The following Tablecompares the uniformities, as deduced from sheet resistancemeasurements, of the three wafers after the deposition of a copper layerhaving a nominal thickness of 1.5 microns. TABLE 1 Non-uniformityEnhance- Standard ment Current deviation Wafer Bath Density (%, 1σ) 1Citrate 3 min. at 7.321 2mA/cm² 2 EDTA 3 min. at 6.233 2mA/cm² 3 None 046.10

[0049] As can be seen from the results in Table 1 above, seed layerenhancement in accordance with the disclosed process provides excellentuniformity (6 to 7%) compared to that without seed layer enhancement(46%). This is consistent with observations during visual examination ofthe wafer after 1.5 micron electroplated copper had been deposited. Suchvisual examination of the wafer revealed the presence of defects atwafer electrode contact points on the wafer without seed layerenhancement.

[0050]FIGS. 5, 6A and 6B are photographs taken using a SEM. In FIG. 5,an ultra-thin seed layer has been deposited on the surface of asemiconductor wafer, including micro-structures, such as trenches 85. Asshown, void regions are present at the lower corners of the trenches. InFIG. 6A, the seed layer has been enhanced in the manner described abovein a bath containing citric acid as the complexing agent. Thisenhancement resulted in a conformal copper seed layer that is verysuited for subsequent electrochemical deposition of coppermetallization.

[0051]FIG. 6B illustrates a seed layer that has been enhanced in a bathcontaining EDTA as the complexing agent. The resulting seed layerincludes larger grain sizes that project as spikes from the sidewalls ofthe trenches. These sidewall grain projections make subsequentelectrochemical deposition filling of the trenches more difficult sincethey localize a higher plating rate resulting in non-uniformity of thesubsequent electrochemical deposition. This effect is particularlynoticeable in recessed micro-structures having small dimensions. Assuch, a complexing agent such as citric acid is more preferable whenfilling small micro-structures. Results comparable for copper bathscontaining citric acid have also been achieved using ED as thecomplexing agent.

[0052]FIG. 7 is a schematic representation of a section of asemiconductor manufacturing line 90 suitable for implementing theforegoing processes. The line 90 includes a vapor deposition tool ortool set 95 and an electrochemical copper deposition tool or tool set100. Transfer of wafers between the tools/tool sets 95 and 100 may beimplemented manually or through an automated transfer mechanism 105.Preferably, automated transfer mechanism 105 transfers workpieces in apod or similar environment. Alternatively, the transfer mechanism 105may transfer wafers individually or in an open carrier through a cleanatmosphere joining the tools/tool sets.

[0053] In operation, vapor deposition tool/tool set 95 is utilized toapply an ultra-thin copper seed layer over at least portions ofsemiconductor workpieces that are processed on line 90. Preferably, thisis done using a PVD application process. Workpieces with the ultra-thinseed layer are then transferred to tool/tool set 100, eitherindividually or in batches, where they are subject to electrochemicalseed layer enhancement at, for example, processing station 110.Processing station 110 may be constructed in the manner set forth inFIG. 3. After enhancement is completed, the workpieces are subject to afull electrochemical deposition process in which copper metallization isapplied to the workpiece to a desired interconnect metallizationthickness. This latter process may take place at station 110, butpreferably occurs at further processing station 115 which deposits thecopper metallization in the presence of an acidic plating bath. Beforetransfer to station 115, the workpiece is preferably rinsed in DI waterat station 112. Transfer of the wafers between stations 110, 112, and115 may be automated by a wafer conveying system 120. Theelectrochemical deposition tool set 100 may be implemented using, forexample, an LT-210™ model or an Equinox™ model plating tool availablefrom Semitool, Inc., of Kalispell, Mont.

[0054] Numerous modifications may he made to the foregoing systemwithout -departing from the basic teachings thereof. Although thepresent invention has been described in substantial detail withreference to one or more specific embodiments, those of skill in the artwill recognize that changes may be made thereto without departing fromthe scope and spirit of the invention as set forth in the appendedclaims.

1. A process for applying a metallization interconnect structure to asemiconductor workpiece, the workpiece including a barrier layerdeposited on a surface thereof, the process comprising the steps of: (a)forming an ultra-thin metal seed layer on the barrier layer, the seedlayer having a thickness of less than or equal to about 500 Angstroms;(b) enhancing the ultra-thin seed layer by depositing additional metalto provide an enhanced seed layer, the enhanced seed layer having athickness at all points on sidewalls of substantially all recessedfeatures distributed within the workpiece that is equal to or greaterthan about 10% of the nominal seed layer thickness over an exteriorlydisposed surface of the workpiece
 2. The process of claim 1 wherein theadditional metal is copper.
 3. The process of claim 1 wherein theultra-thin seed layer is enhanced by a process comprising anelectrochemical deposition step.
 4. The process of claim 3 wherein theelectrochemical deposition step occurs in an alkaline bath.
 5. Theprocess of claim 4 wherein the alkaline bath comprises metal ions and anagent effective in complexing the metal ions.
 6. The process of claim 1wherein the ultra-thin metal seed layer formed in step (a) is formed byphysical vapor deposition.
 7. The process of claim 1 wherein theultra-thin metal seed layer formed in step (a) has a thickness of about50 to about 500 Angstroms.
 8. The process of claim 7 wherein theultra-thin metal layer formed in step (a) has a thickness of about 100to about 250 Angstroms.
 9. The process of claim 1 wherein the complexingagent is comprised of one or more complexing agents selected from EDTA,ED, and polycarboxylic acid.
 10. The process of claim 5 wherein thecomplexing agent is comprised of EDTA and the EDTA in the bath has aconcentration within the range of 0.03 to 1.0 M
 11. The process of claim9 wherein the complexing agent is comprised of ED and wherein the ED inthe electrolytic bath has a concentration within the range of 0.03 to1.0 M.
 12. The process of claim 10 wherein the complexing agent iscomprised of EDTA and the EDTA has a concentration within the range of0.1 to 0.4 M.
 13. The process of claim 9 wherein the complexing agent iscomprised of citric acid and the citric acid in the bath has aconcentration within the range of 0.03 to 1.0 M.
 14. The process ofclaim 4 and further comprising the step of subjecting the semiconductorworkpiece to a further electrochemical deposition process in an acidicelectrolytic solution to complete deposition of the metal to a thicknessneeded for the formation of the interconnect structure.
 15. The processof claim 14 and further comprising the step of subjecting thesemiconductor workpiece to a rinsing process after electrochemicaldeposition in the outline bath and prior to the further electrochemicalcopper deposition process in an acidic electrolytic solution.
 16. In amanufacturing line including a plurality of apparatus for themanufacture of integrated circuits, one or more apparatus of theplurality of apparatus being used for applying a copper metallizationinterconnect structure to a surface of a semiconductor workpiece used toform the integrated circuits, the one or more apparatus comprising:means for applying a conductive ultra-thin seed layer to a surface ofthe semiconductor workpiece; means for electrochemically enhancing theconductive ultra-thin seed layer to render it suitable for subsequentelectrochemical application of the copper interconnect metallization toa predetermined thickness representing a bulk portion of the copperinterconnect metallization structure.
 17. One or more apparatus asclaimed in claim 16 wherein the means for applying is further defined bymeans for applying a conductive ultra-thin copper seed layer to abarrier layer surface of the semiconductor workpiece.
 18. One or moreapparatus as claimed in claim 16 wherein the means for applying isfurther defined by means for applying a conductive ultra-thin copperseed layer to a barrier layer surface of the be semiconductor workpieceusing a PVD process
 19. One or more apparatus as claimed in claim 16wherein the means for applying is further defined by means for applyinga conductive ultra-thin copper seed layer to a barrier layer surface ofthe semiconductor workpiece using a CVD process.
 20. One or moreapparatus as claimed in claim 17 wherein the means for electrochemicallyenhancing the conductive ultra-thin seed layer is further defined bymeans for electrochemically enhancing the conductive ultra-thin seedlayer by electrochemically depositing copper using at alkaline copperbath having a complexing agent.
 21. One or more apparatus as claimed inclaim 20 wherein the electrochemical enhancement of the ultra-thin seedlayer takes place at a plating voltage having a magnitude that is atleast about or greater than 1.1 volts.
 22. One or more apparatus asclaimed in claim 20 wherein the alkaline bath has a pH>or equal to about9.0.
 23. One or more apparatus as claimed in claim 20 wherein thecomplexing agent is comprised of EDTA.
 24. One or more apparatus asclaimed in claim 20 wherein the complexing agent is comprised of ED. 25.One or more apparatus as claimed in claim 20 wherein the completingagent is a comprised of a carboxylic acid or salt thereof.
 26. One ormore apparatus as claimed in claim 25 wherein the complexing agent iscitric acid or salt thereof.
 27. One or more apparatus as claimed inclaim 20 and further comprising means for electrochemically adding afurther layer of copper over the conductive ultra-thin seed layer byelectrochemically depositing copper using an acidic copper bath.
 28. Oneor more apparatus as claimed in claim 27 wherein the electrochemicalenhancement of the ultra-thin seed layer takes place at a platingvoltage having a magnitude that is greater than the magnitude of theplating voltage in the acidic copper bath.
 29. One or more apparatus asclaimed in claim 28 and further comprising means for rinsing thesemiconductor workpiece prior to its introduction to the means forelectrochemically adding a further layer of copper.
 30. A process forapplying a metallization interconnect structure to a semiconductorworkpiece, the workpiece including a barrier layer deposited on asurface thereof, the process comprising the steps of: (a) forming anultra-thin metal seed layer on the barrier layer, the seed layer havinga thickness of less than or equal to about 500 Angstroms; (b) subjectingthe semiconductor workpiece to an electrochemical copper depositionprocess in an alkaline electrolytic bath having copper ions complexedwith a complexing agent such that additional copper is deposited on theultra-thin copper seed layer to thereby enhance the seed layer.
 31. Theprocess of claim 30 wherein the ultra-thin metal seed layer formed instep (a) is formed by physical vapor deposition.
 32. The process ofclaim 30 wherein the ultra-thin seed layer formed in step (a) has athickness of about 50 to about 500 Angstroms.
 33. The process of claim32 wherein the ultra-thin seed layer formed in step (a) has a thicknessof about 100 to about 250 Angstroms.
 34. The process of claim 33 whereinthe ultra-thin seed layer formed in step (a) has a thickness of about200 Angstroms.
 35. The process of claim 30 wherein the alkalineelectrolytic bath has a pH of at least 9.0.
 36. The process of claim 30wherein the copper ions in the electrolytic bath are provided by coppersulfate.
 37. The process of claim 36 wherein the copper sulfate in theelectrolytic bath has a concentration within the range of 0.03 to 0.25M.
 38. The process of claim 36 wherein the concentration of coppersulfate is about 0.1 M.
 39. The process of claim 30 wherein the coppercomplexing agent is comprised of a copper complexing agent selected fromEDTA, ED, and citric acid.
 40. The process of claim 39 wherein thecomplexing agent is comprised of EDTA and the EDTA in the electrolyticbath has a concentration within the range of 0.03 to 1.0 M.
 41. Theprocess of claim 39 wherein the complexing agent is comprised of ED andthe ED in the electrolytic bath has a concentration within the range of0.03 to 1.0 M
 42. The process of claim 39 wherein the complexing agentis comprised of EDTA and the EDTA has a concentration within the rangeof 0.1 to 0.4 M.
 43. The process of claim 39 wherein the complexingagent is comprised of citric acid and the citric acid in theelectrolytic bath has a concentration within the range of 0.03 to 1.0 M.44. The process of claim 43 wherein the citric acid has a concentrationwithin the range of 0.1 to 0.4 M.
 45. The process of claim 30 andfurther comprising the step of subjecting the semiconductor workpiece toa further electrochemical copper deposition process in an acidicelectrolytic solution to complete deposition of the copper to athickness needed for the formation of the copper interconnect structure.46. The process of claim 45 and further comprising the step ofsubjecting the semiconductor workpiece to a rinsing process after step(b) and prior to the further electrochemical copper deposition processin an acidic electrolytic solution.
 47. A semiconductor workpiececomprising: a plurality of the recessed structures distributed in a faceof the semiconductor workpiece; an enhanced seed layer having athickness at all points on sidewalks of substantially all recessedfeatures distributed within the workpiece that is equal to or greaterthan about 10% of the nominal seed layer thickness over an extenorlydisposed surface of the workpiece.
 48. A semiconductor workpiece asclaimed in claim 48 wherein the thickness of the sidewalls ofsubstantially all recessed features is equal to or greater than about20%.